An overview of the migration process from single to multi-core implementations:

1) Architecture analysis - determine the best way to take advantage of multi-core architecture by analyzing your use of:

Interface between Control and Data Planes (and between multiple Data Planes).

External/3rd-party Library usage.

Inter-Process Communications and shared resource usage.

Global variables and resources.

Queuing mechanisms.

Threading mechanisms.

Existing toolchain and build procedures.

2) Board bring-up:

Integrate BSP into Multi-core kernel/executive.

Test and Validation of board and Board Support Package(s).

3) Migrating existing functionality to multi-core:

Partition software and binaries.

Design and create IPC between software components running on different cores.

Efficient synchronization mechanisms to take full advantage of multi-core.

Optimizations specific to multiple data-planes and cores.

4) Testing and Validation:

Check edge conditions and varying-core bringups.

Test for throughput using all cores in sequence from 1 to total number of available cores.

Use cases from our previous development experience:

1) Packet shaping appliance example:

Migrated codebase from monolithic Intel x86 architecture to Cavium Octeon family of processors. We started with a legacy management module and the legacy packet inspection engine running under pSOS. They were moved to 2 separate Octeon cores still running pSOS on each of the 2 cores. This sped up the development process by not significantly changing the codebase. The existing Intel packet driver was converted to a Octeon "simple executable" running on the remaining cores. Product SKU's were extended to encompass a range from a low-end 100Mbps product to a high-end 1Gbps product.

2) Network security appliance example:

Migrated network security software to Cavium Octeon family of processors. The existing software was partitioned into "control plane" and the "data plane". The "control plane" was then ran under vxWorks on one core. The remaining cores were used to run "data plane" portion of the software running as Cavium "simple executives".

3) Infrastructure Wireless Switch example:

Implemented wireless switch functionality on multi-core XLR platform under Linux. All major wireless functionality - AP communication layer, association and authentication, wireless security, packet forwarding was implemented to run load-balanced on multiple cores.

Call or e-mail us for an initial consultation with our engineering staff:

Contact San Jose Engineering about Multi-core Development Services